This invention relates to a trigger circuit for gating on and closing a solid state or semiconductor switch, where the switch requires a d-c triggering pulse.
When a solid state switch, such as a transistor, an SCR (silicon controlled rectifier), a GTO (gate turn off switch), etc., is triggered into conduction, or turned on, by a d-c triggering signal applied to the switch's control terminal or gate, the triggering signal is usually produced by a gate voltage source which is likely to exhibit unwanted voltage variations. This is particularly true when the d-c gate voltage is developed from a-c power line voltage. In addition to source variations, the intrinsic control voltage of the solid state switch, required to obtain control current flow in the switch, may vary from unit to unit. As the d-c triggering signal varies in amplitude, in response to the supply voltage and intrinsic device voltage variations, the power consumed in gating on and closing the switch is apt to vary over a relatively wide range. At times the driving power may be inadequate to properly trigger the solid state switch, while at other times the switch may be overdriven, resulting in a substantial power waste.
The present invention constitutes a significant improvement over the prior trigger circuits since it provides the optimum triggering drive at all times to properly gate a solid state switch into conduction without wasting as much power. This is achieved by a gate driver that always supplies only the precise amount of current required to turn the switch on, and this is accomplished in spite of any gate voltage variations or disturbances.